Meeting the challenge of embedded SRAM

Yervant Zorian and Ken Potts.  
"The first-order challenges of current- and next-generation process device physics, coupled with the astounding complexity that system-on-chip designers confront every day, have transformed the once-well-defined world of embedded SRAM into one of the most vibrant, if least understood, areas in semiconductor technology today. In the device physics domain, the challenges attack on three fronts: process, environment and temporal effects.
Variables that come into play in the complexity domain include memory system architecture; silicon validation requirements; global and local trade-offs for power, performance and area; and SRAM topology optimization to maximize yield. Historically, it has been possible to treat embedded SRAM in a standalone fashion. But today's process and complexity challenges demand that embedded memory be developed as a system to enable robust quality of results while enabling the fastest time-to-market.

In an era when gate oxide thickness can be measured by counting on your fingers the number of atoms, it is obvious that variation on an atomistic scale can affect circuit behavior. Moving up-level to the circuit environment, first-order contributors to variances come from temperature, voltage, noise, electromagnetic interference, self-heating, topology- specific lattice stress and coupling. Finally, the temporal effects of process drift, negative-bias-temperature instability, electromigration and hot carriers must be considered. The figure illustrates the impact of process variations for each new technology node.
Although it is clear that the process mean is scaling well, we must recognize that the systematic and random variations are no longer addressed by traditional design techniques. Traditional signoff with worst-case corner analysis is too aggressive in some cases and too conservative in others; it will negate the benefit of the new process node.
The solution is to employ statistical modeling techniques for predictive worst-case path analysis specific to the foundry process. With good statistical models at the embedded-SRAM designer's disposal, it becomes possible to optimize the circuits to adjust for variance.

Taken in the larger SoC context, the optimum SoC embedded SRAM will employ circuits outside the memory for monitoring and diagnostics. The game is now about achieving the process scaling benefits in the classic quality-of-results categories of area, performance and power through statistical predictability.

With the rising costs of SoC design easily approaching $100 million in some domains, it is incredibly important that the embedded SRAM be silicon-validated; thus the embedded SRAM must be designed in a system context. It is very difficult to validate a memory through a JTAG port without additional circuitry on the test vehicle to exercise the memory in a system context. This circuitry enables at-speed stimulus and employs diagnostics that can be designed with algorithms tailored for the type and topology of the memory under test.

Clearly, running the silicon across process window offset, or split lots, has been a requirement since the 90-nanometer node.

At 65 nm, the techniques for rigorous test of the embedded-SRAM intellectual property emerged that can only be satisfied with embedded-SRAM test chips that mimic systems-on-chip in their size, performance and complexity.
The multimegabit-SoC era emerged at 130 nm, with general usage starting at 90 nm. The key driver in the complexity domain is more embedded-memory area as a percentage of the die area.

Further, most designs today require a tailored memory system that addresses local quality-of-result optimization. There may be caches associated with the embedded processor that need to run blazingly fast, requiring high-speed memory architecture. There may also be a requirement for FIFO stacks that don't need to run fast but that consume significant die area. In this case, high density becomes the architectural choice.

Depending on the system architecture, it is likely that both types of memory will reside in one design and will probably need to support standby and dynamic power control requirements. The key for the embedded-SRAM designer is to design memories that are locally optimized for the desired quality of results while providing observability for system diagnostics and repair.

Over time, embedded-SRAM systems that are fielded with the on-chip diagnostics provide information with respect to yield that feed back into the design process as best practices. Best practices for selecting the right memory topology can be provided to the design engineer, as the empirical data provides a foundation for expected yield analysis on a floor plan basis.

The key to enabling nanometer embedded SRAM to achieve best-in-class quality results is in addressing the system context. In the variation domain, this requires an understanding of the process, environmental and temporal effects that have become essential to the optimization equation. In the complexity domain, the on-chip-intelligence portion of the embedded-memory system provides the engine for in-context silicon validation as well as design-specific algorithms to enable test and repair in the production context. The SoC designer's need for local optimization to meet varying requirements across the system must be addressed.

Finally, the system view of embedded memory requires a deep understanding of yield trade-offs for specific memory combinations on a die.

Embedded SRAM is an inadequate descriptor for an area of technology that surpassed the boundaries of "embedded SRAM" long ago. Today's path to success is through a systems approach".

Yervant Zorian ([email protected]) is vice president and chief scientist at Virage Logic Corp. He chairs the IEEE 1500 standardization working group for embedded-core test. He holds a master's degree from the University of Southern California and a PhD from McGill University. Ken Potts ([email protected]) is vice president of product marketing at Virage Logic. He is a co-inventor on five U.S. patents and holds a BSEE from Montana State University